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Junior/Senior Engg Validation Engg Startup

2 - 6 YearsBengaluru, Hyderabad

Posted: 4 days ago

Job Description

We are looking below skills
FPGA design and validation engineers with working knowledge of high speed protocols or memory subsystems such DDR, QDR etc., Mandatory

VHDL/Verilog programming and working with FPGA is mandatory

C programming is not mandatory. But having experience may have advantage

Emulation experience is a plus.

Experience level we are looking from 2 to 5 years.

Salary: Not Disclosed by Recruiter
Industry: IT-Software / Software Services
Functional Area: Engineering Design, R&D
Role Category: R&D
Role: R&D Executive
Employment Type: Permanent Job, Full Time

Desired Candidate Profile

Education:UG -B.Tech/B.E. - Any Specialization, Computers, Electrical, Electronics/Telecommunication

Company Profile

Connectpro Management Consultants Pvt Ltd.
View Contact Details+
Contact Details

Contact Company:Connectpro Management Consultants Pvt Ltd.

Reference Id:Startup